1. general description 74ahc1g02-q100 and 74ahct1g02-q100 ar e high-speed si-gate cmos devices. they provide a 2-input nor function. the ahc device has cmos input switching leve ls and supply voltage range 2 v to 5.5 v. the ahct device has ttl input switching levels and supply voltage range 4.5 v to 5.5 v. this product has been qualified to the automotive electronics council (aec) standard q100 (grade 1) and is suitable for use in automotive applications. 2. features and benefits ? automotive product qualif ication in accordance with aec-q100 (grade 1) ? specified from ? 40 ? c to +85 ? c and from ? 40 ? c to +125 ? c ? symmetrical output impedance ? high noise immunity ? low power dissipation ? balanced propagation delays ? sot353-1 and sot753 package options ? esd protection: ? mil-std-883, method 3015 exceeds 2000 v ? hbm jesd22-a114f exceeds 2000 v ? mm jesd22-a115-a exceeds 200 v (c = 200 pf, r = 0 ? ) 3. ordering information 74ahc1g02-q100; 74ahct1g02-q100 2-input nor gate rev. 1 ? 6 november 2013 product data sheet table 1. ordering information type number package temperature range name description version 74ahc1g02gw-q100 ? 40 ? c to +125 ? c tssop5 plastic thin shrink small outline package; 5 leads; body width 1.25 mm sot353-1 74ahct1g02gw-q100 74ahc1g02gv-q100 ? 40 ? c to +125 ? c sc-74a plastic surface-mounted package; 5 leads sot753 74AHCT1G02GV-Q100
74ahc_ahct1g02_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserv ed. product data sheet rev. 1 ? 6 november 2013 2 of 12 nxp semiconductors 74ahc1g02-q100; 74ahct1g02-q100 2-input nor gate 4. marking [1] the pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. functional diagram 6. pinning information 6.1 pinning 6.2 pin description table 2. marking codes type number marking [1] 74ahc1g02gw-q100 ab 74ahc1g02gv-q100 a02 74ahct1g02gw-q100 cb 74AHCT1G02GV-Q100 c02 fig 1. logic symbol fig 2. iec logic symbol fig 3. logic diagram mna103 b a y 2 1 4 mna104 4 1 2 1 mna105 b a y fig 4. pin configuration $ + & |